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5-V Low-Drop Fixed Voltage Regulator
TLE 4279
Features * * * * * * * * * Output voltage tolerance 2 % Very low current consumption Early warning Reset output low down to VQ = 1 V Overtemperature protection Reverse polarity proof Settable reset threshold Very low-drop voltage Wide temperature range Ordering Code Package on request Q67006-A9225 P-DIP-8-4 P-DSO-8-1 (SMD) P-DSO-14-4 (SMD) P-DSO-20-6 (SMD) P-DSO-8-1
P-DIP-8-4
Type TLE 4279 A TLE 4279 G
w TLE 4279 GM Q67006-A9307
TLE 4279 GL Q67006-A9306
w New type
Functional Description This device is a voltage regulator with a fixed 5-V output, e.g. in a P-DSO-8-1 package. The maximum operating P-DSO-20-6 voltage is 45 V. The output is able to drive a 150 mA load. It is short circuit protected and the thermal shutdown switches the output off if the junction temperature is in excess of 150 C. A reset signal is generated for an output voltage of VQ < 4.6 V. The reset threshold voltage can be decreased by external connection of a voltage divider. The reset delay time can be set by an external capacitor. If the application requires pull up resistors at the logic outputs (Reset, P-DSO-14-4 Sense Out) the TLE 4269 with integrated resistors can be used. It is also possible to supervise the input voltage by using an integrated comparator to give a low voltage warning.
Semiconductor Group
1
1998-11-01
TLE 4279
Pin Configuration (top view) P-DIP-8-4
S RE D
P-DSO-8-1
1 2 3 4 8 7 6 5
AEP01668
S RE D
1 2 3 4
8 7 6 5
AEP01813
Q SO R GND
Q SO R GND
Pin Definitions and Functions (TLE 4279 A and TLE 4279 G) Pin No. 1 2 3 4 5 6 7 8 Symbol I SI RE D GND R SO Q Function Input; block directly to GND on the IC with a ceramic capacitor. Sense input; if not needed connect to Q. Reset threshold; if not needed connect to ground. Reset delay; to select the delay time, connect to GND via external capacitor. Ground Reset output; open-collector output Sense output; open-collector output 5-V output; connect to GND with a 10 F capacitor, ESR < 10 .
Semiconductor Group
2
1998-11-01
TLE 4279
Pin Configuration (top view)
P-DSO-20-6
RE D N.C. GND GND GND GND N.C. N.C. R 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
AEP01802
S N.C. GND GND GND GND N.C. Q SO
Pin Definitions and Functions (TLE 4279 GL) Pin No. 1 2 4-7, 14-17 10 11 12 19 20 Symbol RE D GND R SO Q I SI Function Reset threshold; if not needed connect to ground. Reset delay; to select delay time connect to GND via external capacitor. Ground Reset output; open-collector output Sense output; open-collector output Output; connect to GND with 10 F capacitor, ESR < 10 Input; block directly to GND at the IC by a ceramic capacitor Sense input; if not needed connect to Q
Semiconductor Group
3
1998-11-01
TLE 4279
Pin Configuration (top view) P-DSO-14-4
RE D GND GND GND GND R 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SI GND GND GND Q SO
AEP02254
Pin Definitions and Functions (TLE 4279 GM) Pin No. 1 2 3, 4, 5, 6 7 8 9 10, 11, 12 13 14 Symbol RE D GND R SO Q GND I SI Function Reset threshold; if not needed connect to GND Reset delay; connect to GND via external delay capacitor for setting delay time Ground Reset output; open-collector output Sense output; open-collector output 5-V output; connect to GND with 10 F capacitor, ESR < 10 Ground Input; block to ground directly at the IC by a ceramic capacitor Sense input; if not needed connect to Q
Semiconductor Group
4
1998-11-01
TLE 4279
Circuit Description The control amplifier compares a reference voltage, made highly accurate by resistance balancing, with a voltage proportional to the output voltage and drives the base of the series PNP transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. In the reset generator block a comparator compares a reference voltage independent of the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V the reset delay capacitor is discharged and the reset output is set to low. This low is guaranteed down to an output voltage of 1 V. As the output voltage increases again, from 4.6 V onward the reset delay capacitor is charged with constant current. When the capacitor voltage reaches the upper switching threshold Vdt, the reset returns to high. By choosing the value of this capacitor, the reset delay time can be selected over a wide range. With the reset threshold input RE it is possible to lower the reset threshold Vrt. If pin RE is connected to pin Q via a voltage divider, for example, the reset condition is reached when this voltage is decreased below the switching threshold Vre of 1.35 V. Another comparator compares the signal of the pin SI, normally fed by a voltage divider from the input voltage, with the reference and gives an early warning on the pin SO. It is also possible to superwise an other voltage e.g. of a second regulator, or to build a watchdog circuit with few external components. Application Description The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor CQ is necessary for the stability of the regulating circuit. Stability is guaranteed at values 10 F and an ESR 10 within the operating temperature range. Both reset output and sense output are open collector outputs and have to be connected to 5 V output via external pull-up resistors 10 k. For small tolerances of the reset delay the spread of the capacitance of the delay capacitor and its temperature coefficient should be noted.
Semiconductor Group
5
1998-11-01
TLE 4279
Error Amplifier Reference Current and Saturation Control
Q
Trimming
D
R
RE
Reference
SO
SI
AEB01955
Block Diagram
Semiconductor Group 6 1998-11-01
TLE 4279
Absolute Maximum Ratings Tj = - 40 to 150 C Parameter Symbol Limit Values min. Input Input voltage Input current Sense Input Input voltage Input current Reset Threshold Voltage Current Reset Delay Voltage Current Ground Current Reset Output Voltage Current Sense Output Voltage Current max. Unit Notes
VI II
- 40
45 -
V -
- internal limited
-
VSI ISI
- 0.3
45 1
V mA
- -
1
VRE IRE
- 0.3 - 10
7 10
V mA
- -
VD ID
- 0.3
7 -
V -
- internal limited
-
IGND
50
-
mA
-
VR IR
- 0.3
7 -
V -
- internal limited
-
VSO ISO
- 0.3
7 -
V -
- internal limited
-
Semiconductor Group
7
1998-11-01
TLE 4279
Absolute Maximum Ratings (cont'd) Tj = - 40 to 150 C Parameter Symbol Limit Values min. 5-V Output Output voltage Output current Temperature Junction temperature Storage temperature Operating Range Input voltage Junction temperature Thermal Data Junction-ambient max. Unit Notes
VQ IQ
- 0.3
7 -
V mA
- -
-5
Tj TStg
-
- 50
150 150
C C
- -
VI Tj
-
- 40
45 150
V C
- -
Rthja
-
100 200 70 70 60 60 30 30
K/W K/W K/W K/W K/W K/W K/W K/W
P-DIP-8-4 P-DSO-8-1 P-DSO-14-4 P-DSO-20-6 P-DIP-8-4 P-DSO-8-1 P-DSO-14-4 P-DSO-20-6
Rthjc
-
Semiconductor Group
8
1998-11-01
TLE 4279
Characteristics VI = 13.5 V; Tj = - 40 C < Tj < 125 C Parameter Symbol Limit Values min. Output voltage Current limit Current consumption; Iq = II - IQ Current consumption; Iq = II - IQ Current consumption; Iq = II - IQ Drop voltage Load regulation Line regulation Reset Generator Switching threshold Reset low voltage Delay switching threshold Switching threshold typ. 5.00 200 150 250 2 0.25 10 10 max. 5.10 500 300 700 8 0.5 30 40 V mA A A mA V mV mV Unit Measuring Condition 1 mA IQ 100 mA 6 V VI 16 V -
VQ IQ Iq Iq Iq Vdr
VQ VQ
4.90 150 - - - - - -
IQ 1 mA, Tj < 85 C IQ = 10 mA IQ = 50 mA IQ = 100 mA1) IQ = 5 mA to 100 mA VI = 6 V to 26 V IQ = 1 mA
Vrt VR Vdt Vst
4.50 - 1.4 0.3 - 3.0
4.60 0.1 1.8 0.45 - 6.5
4.80 0.4 2.2 0.60 0.1 9.5
V V V V V A
-
Rextern = 20 k
- -
Reset delay low voltage VD Charge current
1)
VQ < VRT VD = 1 V
Id
Drop voltage = VI - VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input.)
Semiconductor Group
9
1998-11-01
TLE 4279
Characteristics (cont'd) VI = 13.5 V; Tj = - 40 C < Tj < 125 C Parameter Symbol Limit Values min. Delay time L H Delay time H L Switching voltage Input Voltage Sense Sense threshold high Sence threshold low Sense output low voltage Sense input current typ. 28 1 1.35 max. - - 1.44 ms s V Unit Measuring Condition
td tt Vre
17 - 1.26
CD = 100 nF CD = 100 nF VQ > 3.5 V
Vsi, high Vsi, high VSO,low
1.24 1.16 -
1.31 1.20 0.1
1.38 1.28 0.4
V V V
- -
VSI < 1.20 V; VI > 3 V Rextern = 20 k
-
ISI
-1
0.1
1
A
Semiconductor Group
10
1998-11-01
TLE 4279
Measuring Circuit (P-DIP-8-4, P-DSO-8-1)
V
< t RR
V RT VQ
dV d = dt C D
VDT VST
VD td t RR
V RO
Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output
AED01542
Reset Timing Diagram
Semiconductor Group
11
1998-11-01
TLE 4279
V
< t RR
V RT VQ
dV d = dt C D
VDT VST
VD td t RR
V RO
Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output
AED01542
Sence Input Timing Diagram
Semiconductor Group
12
1998-11-01
TLE 4279
Charge Current Id versus Temperature Tj
d
16 A 14 12 10 8 6 4 2 0 -40
AED01803
Switching Voltage Vdt and Vst versus Temperature Tj
3.2 VD V 2.8
AED01804
V = 13.5 V V C = 1.0 V
V = 13.5 V
2.4 2.0 1.6 1.2 0.8
Vdt
Vst
0.4 0 -40
0
40
80
120 C 160
0
40
80
120 C 160
Tj
Tj
Drop Voltage Vdr versus Output Current IQ
500
AED01805
Reset Switching Threshold Vre versus Temperature Tj
Vre
1.7 V 1.6 1.5 1.4
AED01806
V dr
mV 400
300
Tj = 125 C
200
1.3 1.2
Tj = 25 C
1.1
100
1.0
0
0
30
60
90
120
mA
180
0.9 -40
0
40
80
120 C 160
Q
Tj
Semiconductor Group
13
1998-11-01
TLE 4279
Current Consumption Iq versus Input Voltage VI
30
AED01807
Output Voltage VQ versus Input Voltage VI
12
AED01808
q mA
25
VQ
V 10
20
8
15
RL = 33
6
RL = 50
10
RL = 50 RL = 100 RL = 200
0 10 20 30 40 V 50
4
5
2
0
0
0
2
4
6
8
V 10
V
V
Sense Threshold Vsi versus Temperature Tj
1.6
AED01809
Output Voltage VQ versus Temperature Tj
5.2
AED01671
V si
V 1.5
VQ
V = 13.5 V
V 5.1
V = 13.5 V
1.4 Sense Output High
5.0
1.3
4.9
Sense Output Low 1.2
4.8
1.1
4.7
1.0 -40
0
40
80
120 C 160
4.6 -40
0
40
80
120 C 160
Tj
Tj
Semiconductor Group
14
1998-11-01
TLE 4279
Output Current IQ versus Input Voltage VI
350
AED01810
Current Consumption Iq versus Output Current IQ
12
AED01811
Q mA
300 250
q mA
10
V = 13.5 V Tj = 25 C
Tj = 25 C
200 150 100 50 0
8
Tj = 125 C
6
4
2
0
10
20
30
40 V 50
0
0
20
40
60
80
mA
120
V
Q
Current Consumption Iq versus Output Current IQ
q
1.6 mA 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
AED01812
V = 13.5 V Tj = 25 C
0
10
20
30
40 mA 50
Q
Semiconductor Group
15
1998-11-01
TLE 4279
Package Outlines P-DIP-8-4 (Plastic Dual In-line Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information"
Dimensions in mm
Semiconductor Group 16 1998-11-01
GPD05583
TLE 4279
P-DSO-8-1 (SMD) (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 17
Dimensions in mm
1998-11-01
GPS05121
TLE 4279
P-DSO-20-6 (SMD) (Plastic Dual Small Outline Package)
2.65 max
0.35 x 45
2.45 -0.2
0.2 -0.1
1.27 0.35 +0.15 2) 20 0.2 24x 11 0.1
0.4 +0.8 10.3 0.3
GPS05094
1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 18
0.23 +0.0 9 8 ma x
7.6 -0.2 1)
Dimensions in mm
1998-11-01
TLE 4279
P-DSO-14-4 (SMD) (Plastic Dual Small Outline Package)
0.35 x 45
1.75 max 1.45 -0.2
0.19 +0.06
0.2 -0.1
4 -0.2
1)
1.27 0.35 +0.15 2) 14 0.1 0.2 14x 6 0.2 8 0.4 +0.8
1 7 8.75 -0.21) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side
GPS05093
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 19
8 max.
Dimensions in mm
1998-11-01

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